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30614hk/11714hk 018-13-0068 no.2284-1/26 semiconductor components industries, llc, 2014 march, 2014 ver. 2.2a http://onsemi.com STK672-740AN-E overview the STK672-740AN-E is a hybrid ic for use as a unipolar, 2-phase stepper motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? built-in overcurrent detection function, over heat detection function (output current off). ? fault signal (active low) is output when overcurrent or overheat is detected. ? built-in power on reset function. ?? ? phase signal input driver activated with an active low an d incorpororates a simulataneous on prevention function. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.089 ? : resistor tolerance ? 2%), motor current can be set using two external resistors. ? the enable pin can be used to cut output current while maintaining the excitation mode. ? supports compatible pins with stk672-732an-e. ? specifications absolute maximum ratings at tc = 25 ? c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal ? 0.3 to 6.0 v input voltage vin max logic input pins ? 0.3 to 6.0 v output current 1 iop max 10 s 1 pulse (resistance load) 20 a output current 2 ioh max v dd = 5v, more than 200hz 4.0 a output current 3 iof max 16pin output current 10 ma allowable power dissipation 1 pdmf max with an arbitrarily large heat sink. per mosfet 8.3 w allowable power dissipation 2 pdpk max no heat sink 3.1 w operating substrate temperature tcmax 105 c junction temperature tjmax 150 c storage temperature tstg ? 40 to 125 c thick-film hybrid ic 2-phase stepper motor driver ordering information see detailed ordering and shipping informa tion on page 26 of this data sheet. orderin g numbe r : ena2284a stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
STK672-740AN-E no.2284-2/26 allowable operating ranges at tc=25 ? c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 0 to 42 v operating supply voltage 2 v dd with signals applied 5 ? 5% v input high voltage v ih pins 10, 12, 13, 14, 15, 17, v dd =5 ? 5% 2.5 to v dd v input low voltage v il pins 10, 12, 13, 14, 15, 17, v dd =5 ? 5% 0 to 0.8 v output current 1 i oh 1 tc=105 ? c, more than 200hz , continuous operation, duty=100% 3.0 a output current 2 i oh 2 tc=80 ? c, more than 200hz, continuous operation, duty=100%, see the motor current (i oh ) derating curve 3.3 a recommended operating substrate temperature tc no condensation 0 to 105 ? c recommended vref range vref tc=105 ? c 0.14 to 1.31 v electrical characteristics at tc=25 ? c, v cc =24v, v dd =5.0v *1 parameter symbol conditions min typ max unit v dd supply current i cco v dd =5.0v, enable=low 4.4 8.0 ma output average current *2 ioave r/l=1 ? /0.62mh in each phase 0.519 0.625 0.731 a fet diode forward voltage vdf if=1a (r l =23 ? ) 0.83 1.5 v output saturation voltage vsat r l =23 ? 0.20 0.33 v control input pin input high voltage v ih pins 10, 12, 13, 14, 15, 17 2.5 v dd v input low voltage v il pins 10, 12, 13, 14, 15, 17 ? 0.3 0.8 v 5v level input current i ilh pins 10, 12, 13, 14, 15, 17=5v 50 75 ? a gnd level input current i ill pins 10, 12, 13, 14, 15, 17=gnd 10 ? a fault pin output low voltage v olf pin 16 (i o =5ma) 0.25 0.5 v 5v level leakage current i ilf pin 16 =5v 10 ? a vref input bias current i ib pin 19 =1.0v 10 15 ? a pwm frequency fc 29 45 61 khz overheat detection temperature tsd design guarantee 144 ? c drain-source cut-off current i dss v ds =100v, pins 2, 6, 9, 18=gnd 1 ? a notes *1: a fixed-voltage power supply must be used. *2: the value for ioave assumes that the lead frame of the product is soldered to the mounting circuit board. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
STK672-740AN-E no.2284-3/26 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 102030405060708090100110 moter current ioh a operation substrate temperature tc c 200hz 2ex hold notes ?? the current range given above represents conditions wh en output voltage is not in the avalanche state. ?? if the output voltage is in the avalan che state, see the allowable avalanche en ergy for stk672-7** series hybrid ics given in a separate document. ?? the operating substrate temperature, tc, given abov e is measured while the motor is operating. because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. ?? the tc temperature should be checked in the cent er of the metal surface of the product package. derating curve of motor current, i oh, vs. STK672-740AN-E operating substrate temperature, tc
STK672-740AN-E no.2284-4/26 block diagram fao ai bi vss current control chopper circuit over current fault signal (open drain) over heating detection latch circuit vdd=5v
STK672-740AN-E no.2284-5/26 measurement circuit (the terminal which is not appointed is open. the m easurement circuit of stk672- 740an-e is the same as stk672-732an-e.) 10 12 17 19 13 15 14 6 5 7 3 1 a a gnd 5v 1v iill iib 16 2 18 9 iilf iilh 5v gnd stk672- 74xan-e 2. iilf,iilh,iill,iib 13 17 12 10 15 14 19 2 5 7 3 1 stk672- 74xan-e v 24v 23 gnd vdf 96 16 18 1. vdf 10 17 12 19 13 15 14 6 5 7 3 1 v gnd vsat 24v 23 5v 5v 2 18 16 9 stk672- 74xan-e 3. vsat 10k 1k 7.5k a 5v icco gnd 24v 100 1 0.62mh ioave ioave fc 12 19 13 15 14 6 5 7 3 1 2 18 16 9 17 10 sw close sw at mesurement of volf 910 volf stk672- 74xan-e 4. icco, ioave, fc,volf
STK672-740AN-E no.2284-6/26 sample application circuit precautions [gnd wiring] ?? to reduce noise on the 5v/24v system, be sure to place the gnd of c01 in the circuit give n above as close as possible to pin 2 and pin 6 of the hybrid ic. in addition, in order to set the current accurately, the gnd si de of ro2 of vref must be connected to the shared ground terminal used by the pin 18 (s.g) gnd, p.g1 and p.g2. [input pins] ?? if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to s. gnd, pin 18. measures must also be taken so that a voltage equal to or greater than v dd is not input. ??? do not wire by connecting the circuit pattern on the p.c.b side to pins 4, 8, or 11 on the n.c. shown in the internal block diagram. ?? apply 2.5v high level input to pins 10, 12, 13, 14, 15, and 17. ?? since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17 are used as inputs, a 1 to 20k ? pull-up resistor (to v dd ) must be used. at this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.8v at low level (less than 0.8v at low level when i ol =5ma). [current setting vref] considering the specifications for the vref in put bias current iib, we recommend a value 1k ? or less for r02. if the motor current is temporarily reduced, the circuit given below(stk672-740an: i oh >0.3a) is recommended. 5v r01 r02 r3 5v r02 r3 vref vref r01 stk672 -74xan-e + 9 13 17 12 10 15 14 16 19 18 6 2 7 5 1 3 v dd (5v) a ab b bb enable resetb fault a ab b bb vref r01 r03 r02 s.g p.g1 p.g2 p.gnd v cc 24v c01 at least 100 ? f 2 phase stepper motor driver + c02 10 ? f
STK672-740AN-E no.2284-7/26 [setting the motor current] the motor current, i oh , is set using the pin 19 voltage, vref, of the hybrid ic. equations related to i oh and vref are given below. vref ?? (ro2 ? (ro2+ro1)) ? v dd (5v) (1) i oh ? (vref ? 4.9) ? rs (2) the value of 4.9 in equation (2) above represents the vref voltage as divided by a circuit inside the control ic. rs : 0.089 ? (current detection resistor inside the hybrid ic) ioh 0 [smoke emission precuations] if pin 18 (s.g terminal) is attached to the board without using solder, overcurrent may flow into the mosfet at v cc on (24v on), causing the stk672-740 an-e to emit smoke because 5v circuits cannot be controlled. in addition, as long as one of the output pins, 1, 3, 5, or 7, is open, inductance energy stored in the motor results in electrical stress on the driver, possibly resulting in the emission of smoke. input pin functions pin name pin no. function input conditions when operating a 13 phase signal input of 5pin (phase a output). low active(with a function to prevent simultaneous on of a and ab ,or b and bb. ab 17 phase signal input of 7pin (phase ab output). b 12 phase signal input of 3pin (phase b output). bb 10 phase signal input of 1pin (phase bb output). resetb 14 system reset initial state of a and bb phase excitation in the timing charts is set by switching from low to high. a reset is applied by a low level enable 15 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low-level input. output pin functions pin name pin no. function input conditions when operating fault 16 monitor pin used when over-current detection or overheat detection function is activated. low level is output when detected. note : see the timing chart for the concrete details on circuit operation.
STK672-740AN-E no.2284-8/26 timing charts 2-phase excitation power on reset (or resetb) vdd a ab b bb enable fao fab fbo fbb 1-2 phase excitation power on reset (or resetb) vdd a ab b bb enable fao fab fbo fbb
STK672-740AN-E no.2284-9/26 1-2 phase excitation (enable) output off power on reset (or resetb) vdd a ab b bb enable fao fab fbo fbb 1-2 phase excitation (hold operation results during fixed clock) hold operation power on reset (or resetb) vdd a ab b bb enable fao fab fbo fbb
STK672-740AN-E no.2284-10/26 package dimensions unit : mm sip19 29.2x14.4 case 127cf issue o 1 19
STK672-740AN-E no.2284-11/26 STK672-740AN-E technical data 1. input pins and functional overview 2. STK672-740AN-E over current detection, thermal shutdown detection. 3. STK672-740AN-E allowable avalanche energy 4. STK672-740AN-E internal loss calculation 5. thermal design 6. package power loss pdpk derating curve for the ambient temperature ta 7. example of stepper motor driver outp ut current path (1-2 phase excitation) 8. other usage notes
STK672-740AN-E no.2284-12/26 1. i/o pins and functions of the control bloc k [pin description] hic pin pin name function 14 resetb system reset 15 enable motor current off 16 fault overcurrent/over-heat detection output 19 vref current value setting description of each pin 1-1.[resetb (system-wide reset)] the reset signal is formed by th e power-on reset function built into the hic and the resetb terminal. when activating the internal circuits of the hic using the pow er-on reset signal within the hic, be sure to connect pin 14 of the hic to v dd . 1-2. [enable (forcible off control of excitation drive output a, ab, b, and bb, and selecting operation/hold status inside the hic)] enable=1: normal operation when enable=0: motor current goes off, and exc itation drive output is forcibly turned off. the system clock inside the hic stops at this time, with no effect on the hic even if input pins other than reset input vary. in addition, since current does not flow to the motor, the motor shaft becomes free. if the ? a to ? bb signal input used for motor rotation suddenly stops, the motor shaft may advance beyond the control position due to inertia. a slow down setting where the ? a to ? bb signal input cycle gradually decreases is required in order to stop at the control position. 1-3. [fault] fault is an open drain output. it outputs low le vel when overcurrent, or overheat is detected. 1-4. [vref (voltage setting to be us ed for the current setting reference)] input voltage is in the voltage range of 0.14v to 1.31v. the recommended vref voltage is 0.14v or higher because the output offset voltage of vref/4.9 amplifier cannot be controlled down to 0v. note: ? pin type is analog input configuration and input pull-down resistance 100 k ? . the internal impedance 100 k ? is designed so that the increase in current is prevented while pin 19 is open. 1-5. [input timing] the control ic of the driver is equipped with a power on reset function capable of initializing internal ic operations when power is supplied. a 4v typ settin g is used for power on reset. because the specification for the mosfet gate voltage is 5v ? 5%, conduction of current to output at the time of power on reset adds electromotive stress to the mosfet due to lack of gate voltage. to prevent electromotive stress, be sure to set enable=low while v dd , which is outside the operating supply voltage, is less than 4.75v. resetb, enable, ? a to ? bb signals input timing 4vtyp 3.8vtyp no time specification no time specification no time specification control ic power (v dd ) rising edge control ic power on reset resetb signal input enable signal input a to bb signal input
STK672-740AN-E no.2284-13/26 1-6. [configuration of control block i/o pins] input pins 13,17,12,10,15,14pin vdd vss 10k ? 100k ? inp ut p in the input pins of this driver all use schmitt input. typical specifications at tc=25 ? c are given below. hysteresis voltage is 0.3v (viha-vila). input voltage specifications are as follows. v ih =2.5vmin v il =0.8vmax output ? pin pin16 vdd vss overheating overcurrent vref/4.9 vss amplif ier input pin pin19 vss 100k ? viha when rising when falling 1.5vtyp vila 1.8vtyp input voltage
STK672-740AN-E no.2284-14/26 2. overcurrent detection, overheat detection functions each detection function operates using a latch system and turns output off. because a reset signal is required to restore output operations, once the power supply, v dd , is turned off, you must either again apply power on reset with v dd on or apply a resetb=high ? low ? high signal. 2-1.[overcurrent detection] this hybrid ic is equipped with a function for detecting over current that arises when the motor burns out or when there is a short between the motor terminals. overcurrent detection occurs at 3.5a typ with the stk672-732an-e, and 5.5a typ with the STK672-740AN-E. overcurrent detection begins after an interval of no detection (a dead time of 5.5 ? s typ) during the initial ringing part during pwm operations. the no detection interval is a period of time where overcurrent is not detected even if the current exceeds i oh . 2-2. [overheat detection] rather than directly detecting the temperature of the semi conductor device, overheat detection detects the temperature of the aluminum substrate (144 ? c typ). within the allowed operating range recommended in the specifi cation manual, if a heat sink attached for the purpose of reducing the operating substrate temp erature, tc, comes loose, the semic onductor can operate without breaking. however, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding i oh max that occurs before over current detectio n is activated. set motor current, i oh pwm period no detection interval (5.5 ? s typ) 5.5 ? mosfet all off i oh max normal operation operation when motor pins are shorted current when motor terminals are shorted overcurrent detection
STK672-740AN-E no.2284-15/26 3. allowable avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepper motor with constant current chopping using an stk672-7** series hybrid ic, the waveforms shown in figure 1 below result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-7** series when driving a 2-phase motor with constant current chopping when operations of the mosfet built into stk672-7** series ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (3-1). eavl1=v dss ? iavl ? 0.5 ? tavl ------------------------------------------- (3-1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (3-1) is a constant require d to convert the iavl triangle wave to a square wave. during stk672-7** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy , eavl, is therefore represented by equation (3-2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (3-1). pavl=v dss ? iavl ? 0.5 ? tavl ? fc -------------------------------- (3-2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate the stk672-7** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 ? s, the result is: pavl=110 ? 1 ? 0.5 ? 0.2 ? 10 -6 ? 50 ? 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calcu lating equation (3-2) falls within the allowable range for avalanche operations. i oh : motor current peak value tavl: time of avalanche operations iavl: current during avalanche operations vdss: voltage during avalanche operations
STK672-740AN-E no.2284-16/26 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness cau sed by the circuit pattern of the board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-7** series when driving a 2-phase stepper motor with constant current chopping 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 01234 average power loss pavl during avalanche pavl w motor current, ioh a tc=105c tc=80c note : the operating conditions given above represent a loss when driving a 2-phase stepper motor with constant current chopping. because it is possible to apply 3w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. i oh : motor current peak value figure 3 allowable loss range, pavl-i oh during STK672-740AN-E avalanche operations pavl-ioh
STK672-740AN-E no.2284-17/26 4. calculating STK672-740AN-E hic internal power loss the average internal power loss in each excitation mode of the STK672-740AN-E can be calculated from the following formulas. *1 each excitation mode 2-phase excitation mode 2pdavex=(vsat+vdf) ? (1/(t1+t2+t3)) ? ioh ? t2+(1/(t1+t2+t3)) ? ioh ? (vsat ? t1+vdf ? t3) 1-2 phase excitation mode 1-2pdavex=(vsat+vdf) ? (1/(t1+t2+t3)) ? ioh ? t2+(1/(t1+t2+t3)) ? ioh ? (vsat ? t1+vdf ? t3) motor hold mode holdpdavex= (vsat+vdf) ? i oh vsat : combined voltage represented by the ron voltage drop+shunt resistor vdf : combined voltage represented by the mosfet body diode+shunt resistor t1, t2, and t3 represent the waveforms shown in the figure below. t1 : time required for the winding current to reach the set current (i oh ) t2 : time in the constant current control (pwm) region t3 : time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.20)) ln (1-(((r+0.20)/v cc ) ? i oh )) t3= (-l/r) ln ((v cc +0.20)/(i oh ? r+v cc +0.20)) v cc : motor supply voltage (v) l : motor inductance (h) r : motor winding resistance ( ? ) i oh : motor set output current crest value (a) for the values of vsat and vdf, be sure to substitute from vsat vs i oh and vdf vs i oh at the setting current value i oh . (see pages to follow) then, determine if a heat sink is necessary by comparing with the ? tc vs pd graph (see next page) based on the calculated average output loss, hic. for heat sink design, be sure to see ?5. thermal design?. the hic average power, pdavex described above, represents loss when not in avalanche mode. to add the loss in avalanche mode, be sure to add pavl using the formula (for average power loss , pavl, for stk672-7** during avalanche mode, described below to pdavex described above.) when using this ic without a fin, always check for temp erature increases in the set, because the hic substrate temperature, tc, varies due to e ffects of convection around the hic. ioh 0 a t1 t2 t3
STK672-740AN-E no.2284-18/26 4-2. [calculating the average power loss, pavl, during avalanche mode] the allowable avalanche energy, eavl, during fixed current chopping operation is represented by equation (3-2) used to find the average power loss, pavl, during avalanche mode that is calculated by multiplying equation (3-1) by the chopping frequency. pavl=v dss ? iavl ? 0.5 ? tavl ? fc (3-2) fc : hz units (fc is set to the pwm frequency of 50khz.) be sure to actually operate an stk672-7** series and substitute values found when observing operations on an oscilloscope for v dss , iavl, and tavl. the sum of pavl values for each excitation mode is multip lied by the constants given below and added to the average internal hic loss equation, except in the case of 2-phase excitation. 1-2 excitation mode and higher: pavl(1)=0.7 ? pavl (4-1) during2-phase excitation mode and motor hold: pavl(1)=1 ? pavl (4-2)
STK672-740AN-E no.2284-19/26 0 0.2 0.4 0.6 0.8 1 00.511.522.533.544.5 output saturation voltage vsat - v output current, ioh - a STK672-740AN-E output saturation voltage vsat vs. output current tc=25 c tc=105 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 00.511.522.533.544.5 forward voltage, vdf - v output current, ioh - a STK672-740AN-E forward voltage, vdf -output current, ioh tc=25 c tc=105 c 0 10 20 30 40 50 60 70 80 00.511.522.533.5 substrate temperature rise, ? tc - ? c hybrid ic internal average power dissipation, pdav - w substrate temperature rise, ? tc (no heat sink) - internal average power dissipation, pdav
STK672-740AN-E no.2284-20/26 5. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current increases. to calculate pdav, refer to ?calculating internal hic loss? in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, figure 1 motor current timing t1 : motor rotation operation time t2 : motor hold operation time t3 : motor current off time t2 may be reduced, depending on the application. t0 : single repeated motor operating cycle i o 1 and i o 2 : motor current peak values due to the structure of motor windings, the phase curren t is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 ? p1+t2 ? p2+t3 ? 0) ? to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 ? c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of ? c-a in equation (ii) below and the graph depicted in figure 3. ? c-a= (tc max-ta) ? pdav ---------------------------- (ii) tc max : maximum operating substrate temperature =105 ? c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 ? c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (3-2), ?allo wable stk672-7** avalanche energy value?, to pdav. io1 io2 -io1 0 a t1 t2 t3 t0 motor phase current (sink side)
STK672-740AN-E no.2284-21/26 figure 2 0 10 20 30 40 50 60 70 80 00.511.522.533.5 substrate temperature rise, ? tc - ? c hybrid ic internal average power dissipation, pdav - w substrate temperature rise, ? tc (no heat sink) - internal average power dissipation, pdav figure 3 1 10 100 10 100 1000 heat sink thermal resistance, c -a- ? c / w heat sink area, s cm2 (thickness : 2mm) heat sink area (board thickness: 2mm) - ? c-a no surface finish surface finished in black
STK672-740AN-E no.2284-22/26 6. mitigated curve of package power lo ss, pdpk, vs. ambient temperature, ta package power loss, pdpk, refers to the average internal power loss, pdav, allowable without a heat sink. the figure below represents the allowable power loss, pd pk, vs. fluctuations in the ambient temperature, ta. power loss of up to 3.1w is allowable at ta=25 ? c, and of up to 1.75w at ta=60 ? c. * the package thermal resistance c-a is 25.8c/w. 0 0.5 1 1.5 2 2.5 3 3.5 0 20406080100120 allowable power dissipation, pdpk - w ambient temperature, ta - c allowable power dissipation, pdpk (no heat sink) - ambient temperature, ta
STK672-740AN-E no.2284-23/26 7. example of stepper moto r driver output current path (1-2 phase excitation) 24v 2 phase stepper motor p.gnd c02 vcc ioa ioab pwm o p eration ab(pin 17) a(pin 13) fao ai bi vss fault signal (open drain) over heat detection vdd vref f1 f2 f3 f4 p.g2 fab fbo fbb fault r1 r2 a p.g1 vss vref /4.9 vss 100k amp ab b bb bbin bin abin ain enable resetb wh en pwm o perations of ioa are off, for ioab, negative current flows through the parasitic diode, f2. when pwm operations of ioab are off, for ioa, negative current flows through the parasitic diode, f1. phase a output current ioa phase ab output current ioab latch at least 100 ? f + chopper circuit over current detection latch po wer o n reset
STK672-740AN-E no.2284-24/26 8. other usage notes in addition to the ?notes? indicated in the sample application circuit, care should also be given to the following contents during use. (1) allowable operating range operation of this product assumes use within the allowabl e operating range. if a supply voltage or an input voltage outside the allowable operating range is applied, an overvoltage may damage the internal control ic or the mosfet. if a voltage application mode that exceed s the allowable operating range is antic ipated, connect a fuse or take other measures to cut off power supply to the product. (2) input pins if the input pins are connected directly to the board connectors, el ectrostatic discharge or other overvoltage outside the specified range may be applied from the connectors and may damage the product. current generated by this overvoltage can be suppressed to effectively prevent damage by inserting 100 ? to 1k ? resistors in lines connected to the input pins. take measures such as inserting resistors in lines connected to the input pins. (3) power connectors if the motor power supply v cc is applied by mistake without connecting the gnd part of the power connector when the product is operated, such as for test purposes, an overcurrent flows through the v cc decoupling capacitor, c1, to the parasitic diode between the v dd of the internal control ic and gnd, and may damage the power supply pin block of the internal control ic. to prevent damage in this case, connect a 10 ? resistor to the v dd pin, or insert a diode between the v cc decoupling capacitor c1 gnd and the v dd pin. (4) input signal lines 1) do not use an ic socket to mount the driver, and instead solder the driver directly to the board to minimize fluctuations in the gnd potential due to the influence of the resistance component and inductance component of the gnd pattern wiring. 2) to reduce noise caused by electromagnetic induction to small signal lines, do not design small signal lines (sensor signal lines, and 5v or 3.3v power supply signal lines) that run parallel in close proximity to the motor output line a (pin 5), ab (pin 7), b (pin 3), or bb (pin 1) phases. bb b ab a r1 r2 vdd gnd vdd=5v 5 7 3 1 vss 2 9 a ab b bb vref s.g c1 vcc open 24v reg . fault 6 enable resetb overcurrent path overcurrent protection measure: insert a resistor overcurrent protection measure: insert a diode fao fabo fbo fbbo ai bi vref 5v reg. .
STK672-740AN-E no.2284-25/26 (5) when mounting multiple drivers on a single board when mounting multiple drivers on a single board, the gnd design should mount a v cc decoupling capacitor, c1, for each driver to stabilize the gnd poten tial of the other drivers. the ke y wiring points are as follows. (6) v cc operating limit when the output (for example f1) of a 2-phase stepper motor driver is turned off, the ab phase back electromotive force eab produced by current flowing to the paired f2 para sitic diode is induced in the f1 side, causing the output voltage vfb to become twice or more the v cc voltage. this is expressed by the following formula. vfb = v cc + eab = v cc + v cc + i oh x rm + vdf (1.5v) v cc : motor supply voltage, i oh : motor current set by vref vdf: voltage drop due to f2 parasitic diode and current detection resistor r1, rm: motor winding resistance value using the above formula, make sure that vfb is always less than the mosfet withstand voltage of 100v. this is because there is a possibility that operating limit of v cc falls below the allowable operating range of 42v, due to the rm and i oh specifications. the oscillating voltage in excess of vfb is caused by l crm (inductance, capacitor, re sistor, mutual inductance) oscillation that includes micro capacitors c, not present in the circuit. since m is affected by the motor characteristics, there is some difference in oscillating voltage according to th e motor specifications. in add ition, constant voltage drive without constant current drive enables motor rotation at v cc ? 0v. f1 on f2 off v cc r1 m f1 off f2 off v cc r1 m gnd gnd a p hase ab phase ab p hase a p hase vfb v cc eab current path current path eab eab is generated by the mutual induction m. 24v gnd 5v gnd 9 9 9 18 18 18 19 19 19 2 6 2 6 2 6 input signals ic1 ic2 ic3 motor 1 thick and short short thick motor 2 motor 3 input signals input signals
STK672-740AN-E ps no.2284-26/26 ordering information device package shipping (qty / packing) STK672-740AN-E sip-19 (pb-free) 15 / tube on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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